The invention generally relates to a semiconductor device. More particularly, the invention relates to a vertical floating body cell and a method for fabricating the same.
Efforts have been made to overcome limitations of a cell structure including a transistor and a capacitor. For example, a capacitor that inhibits the high integration of a memory is eliminated, and a memory cell is configured to have a transistor, which is referred to as a floating body cell (FBC) structure. The FBC structure utilizes a floating body effect phenomenon that changes a threshold voltage when charges are accumulated in a channel bottom of the transistor.
When holes are injected or accumulated into a NMOS, a floating body effect is generated to lower the threshold voltage of the channel and increase the current of the transistor. In FBC, a silicon-on-insulator (SOI) substrate is required so that the holes in the bottom of the channel may be retained for a long period of time. The detailed structure and operation of the FBC are explained with reference to “Floating body RAM technology and its scalability to 32 nm node and beyond” (T. Shino et al., IEDM, 2006).
In DRAM a capacitor is connected to a cell transistor, and a complicated process is required to form the structure. Also, a high thermal treatment process is required to improve a characteristic of the transistor. The FBC technology may skip the above-described complicated process so that a device may be highly integrated. The FBC technology facilitates an embodiment of an embedded DRAM including a logic circuit without a capacitor, thereby being useful in various applications.
If a channel length becomes shorter in the FBC having a plane transistor, an area where charges can be accumulated is reduced. Also, generated charges are recombined into source/drain regions so that it is difficult to retain data. As a result, it is difficult to reduce the size of the transistor. The usage of the SOI wafer increases manufacturing costs, thereby limiting commercialization of FBCs.